1. Field of the Invention
This invention relates generally to integrated circuit memory device, and, more particularly, to enhancing the access times of such integrated circuit memory devices.
2. Background of the Invention
Often one of the limitations in the access time for memory devices having bitlines, such as Random Access Memories (RAMs), Static Random Access Memories (SRAMs) and nonvolatile memories like Erasable Programmable Read Only Memories (EPROMs), Erasable Programmable Read Only Memories (EEPROMs), and Flash EPROMs, is the recovery time of the bitlines at the end of a write operation that characterizes such devices. During a write operation of a SRAM, for instance, one bitline of the bitline pair is typically pulled to a low logic state while the other bitline of the bitline pair remains at a high logic state. At the end of the write operation, the bitline that is a low logic state is pulled to the high logic state by equilibrate circuitry so that the bitline true and complement of the bitline pair are shorted together. This shorting together of the bitlines of the bitline pair and pulling them to a supply voltage, such as Vcc, is referred to as the "recovery" of the bitlines.
An example of a memory structure 10, with one or more memory cells and associated circuitry is illustrated in the schematic diagram of FIG. 1. In this example, memory structure 10 is representative of a SRAM with the differential bitline pair 12, 14. Memory cells 16 reside between bitline true (BLT) 12 and bitline complement (BLC) 14 and includes n-channel pass transistor 17 having a source/drain path connected on one side to bitline true 12 and n-channel transistor 18 having a source/drain path connected on one side to bitline complement 14. The gates of pass transistors 17 and 18 are connected to and controlled by wordline signal 19. The drains of n-channel cell transistors 20, 22 are connected to the second side of the source/drain paths of pass transistors 17, 18, respectively; in cross-coupled fashion, the drain of cell transistor 20 is connected to the gate of gate of cell transistor 22, and vice versa. The sources of cell transistors 20, 22 are biased to ground. Memory cell node 21 is defined as the electrical connection of the drain of cell transistor 20 and the gate of cell transistor 22, and memory cell node 23 is defined as the electrical connection of the drain of cell transistor 22 and the gate of cell transistor 20. While a 4-T memory cell 16 is shown in FIG. 1, other types of memory cells, such as 6-T memory cells or memory cells with only one bitline, may be used.
In conjunction with memory cells 16, memory structure 10 also features column passgates 36, 38, 46 and 48. Bitline true pass transistor 36 and bitline complement pass transistor 38 have source/drain paths connected on a first side to bitline true 12 and bitline complement 14, respectively, and gates connected to and controlled by column decode signal 32. The source/drain path of pass transistor 36 is connected a second side to write driver circuitry 40 via write bus true (WBT) 42 and the source/drain path of pass transistor 38 is connected on its other side to write driver circuitry 40 via write bus complement (WBC) 44. A first source/drain of bitline true pass transistor 46 is coupled to BLT 12 and a second source/drain is coupled to sense amplifier circuitry 50 via read bus true (RBT) 54. A first source/drain of bitline complement transistor 48 is coupled to BLC 14 and a second source/drain is coupled to sense amplifier circuitry 50 via read bus complement (RBC) 52. The gates of column passgates 46, 48 are controlled by signal 35, the inverse of column decode signal 32 generated as an output signal of inverter 34.
The column of memory structure 10 is selected upon column decode signal 32 being driven to a high logic level (1), turning on pass transistors 36, 38. Writes according the Data 56 provided to Write Driver 40 may then be accomplished by appropriate manipulation of WBT 42 and WBC 44 by Write Driver 40, and thus of column passgates 36, 38 and BLT 12 and BLC 14, when wordline 19 is a high logic level. Either BLT 12 or BLC 14 of the differential bitline pair is pulled low (0) while the other bitline remains high (1) for the duration of the write operation.
After the write operation, wordline 19 is turned off and the bitline that was pulled low is now pulled to a high logic level and the bitline pair is typically shorted together and pulled to Vcc. Equilibration transistor devices 24, 26, and 28 assist in this recovery of the differential bitline pair. Equilibration transistors 24, 28 each have a first source/drain that is coupled to voltage supply Vcc; a second source/drain of 24 is coupled to BLT12 and equilibration transistor 26 and a second source/drain of 28 is coupled to BLC 14 and equilibration transistor 26 as shown. The gates of equilibration transistors 24, 26, and 28 are connected to and controlled by edge transition detection (ETD) signal 30. ETD signal 30 is generated in response to the transition of some external memory signal, such as an address signal or a control signal supplied to the memory device. Upon the ETD signal 30 transitioning to a true logic state (0), equilibrate devices 24, 26, 28 are controlled to pull up the bitline that went to a logic low level for the duration of the write operation.
Recovery of the bitlines of a memory device is slowed considerably by the capacitance of the bitlines. Bitlines of a contemporary SRAM device, for instance, may each be characterized as having capacitance of approximately 1 pF to 4 pF or more. The equilibrate transistors of the memory device assist to pull up the low bitline but their relatively small size, on the order of approximately 5 microns, for instance, may delay the time required to pull-up a bitline characterized as having the capacitance noted above. What is needed in the art is to be able to more quickly recover the differential bitline pair following the completion of a write operation so as to enhance the access time of the memory device.